1. Field of the Invention
The present invention generally relates to integrated semiconductor devices, such as metal-oxide semiconductors (MOS), and more particularly to a low-voltage complementary metal-oxide semiconducting (CMOS) differential amplifier.
2. Description of the Related Art
Logic circuits, such as those used in computer processors and other conventional microelectronics, depend upon electrical signals which are one of two voltage states, "high" or "low." The exact voltage of a high or low signal may vary considerably, and circuits are designed to be tolerant of margins about a nominal value. For example, conventional transistor-transistor-logic (TTL) logic levels use a voltage threshold of 1.4 volts, with a margin of 0.6 volts about the threshold, i.e., a high-voltage state can be as low as 2.0 volts, and a low-voltage state can be as high as 0.8 volts. In contrast, conventional circuitry using complementary metal-oxide semiconducting (CMOS) technology typically provides a voltage threshold between 2.0 and 3.0 volts. CMOS technology provides certain advantages over bipolar transistors, but the two types of transistors are often combined in a logic circuit. Thus, when using CMOS circuitry, it is necessary to translate voltage states from TTL logic levels to CMOS logic levels. Various types of buffers or amplifiers are used to couple such differing logic circuits and appropriately shift input voltage levels to be compatible with the output circuitry.
Prior-art logic level translators include both single-ended amplifiers and differential amplifiers. A single-ended amplifier simply has one input and one output, while a differential amplifier has two inputs and two outputs, the states of a given input or output pair being complementary, i.e., one being high and the other low. Differential amplifiers have several advantages over single-ended amplifiers and are commonly used to amplify analog, as well as digital, signals. Differential CMOS amplifiers can also be used as operational amplifiers, comparators, sense amplifiers and front-end buffers for other circuits, and are particularly useful for linear amplification with a minimum of distortion.
One CMOS differential amplifier is disclosed in U.S. Pat. No. 4,937,476, and is also discussed in the article "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 165-68 (February 1991). A representative circuit constructed according to that invention is shown in FIG. 1, wherein an input buffer uses a self-biased differential amplifier. The differential amplifier has a first pair of complementary N- and P- type field effect transistors (FETs) coupled to the input signal (V.sub.IN+), and a second pair of complementary N- and P- type FETs coupled to a reference voltage (V.sub.IN-). The first and second pairs of FETs are coupled to a supply voltage (V.sub.dd) that is controlled by a third pair of complementary FETs. The drains of the first set of FETs are connected to the gates of the third set of FETs, to create a negative feedback within the amplifier. The bias voltage of the first set FETs is set at the midpoint of the active region. If the bias voltage moves from the midpoint (e.g., due to variations in temperature), the feedback from the first FETs to the third FETs will vary the supply voltage so that the bias voltage is returned to the center of the active region. This circuit has a single output; for a time differential output, the circuit is duplicated with the input signals cross-wired, providing two outputs. See also U.S. Pat. Nos. 4,958,133 and 5,278,467.
The foregoing design still has certain limitations. Typical high- or low-threshold voltage (V.sub.t) devices have relatively narrow channel-length modulation characteristics and, accordingly, analog current sources have limited common-mode power supply rejection ratios (CMRR). Delay variations can also occur due to the NFET and PFET impedance ranges. PFETs, as configured in the prior-art, can further exhibit undesirable body-effect sensitivity arising from voltage variations in the FET substrate. Rise time signal quality is relatively quick in these devices, but there is still room for improvement with lower power supplies, i.e., rise time can be slower where power is supplied via a battery. It would, therefore, be desirable and advantageous to devise a CMOS differential amplifier which would overcome the foregoing limitations.